1. Field of the Invention
This invention relates generally to integrated circuit memory devices, and more particularly to an architecture for implementing a memory device which includes an array of memory cells sub-divided into array blocks wherein amplification of data signals received from the array blocks is necessary for improving memory performance.
2. Description of the Prior Art
Semiconductor memory devices include arrays of memory cells for storing data wherein each memory cell typically stores a single data bit. Upon reading data from a memory cell, stored charge flows from the cell to generate a data signal transmitted via a bit line. A certain time interval is required to reach a peak power level for the data signal.
FIG. 1 shows a circuit block diagram of a prior art semiconductor integrated circuit memory device (IC memory device 10) including a plurality of array blocks 12 arranged in array block rows 14, and a plurality of input/output pads (I/O pads) 15. Each array block 12 includes a plurality of memory cells (not shown) arranged in rows and columns as further explained below. Each array block row 14 includes: a number N of the array blocks 12; a row decoder 16 coupled to each array block in the corresponding array block row via row address lines 18; N column decoders 20 each coupled to one of the array blocks 12 via a corresponding set of column address lines 22; N block sense amplifiers 24 each coupled to receive memory data from one of the array blocks 12 via data lines 26; and a global sense amplifier 28 coupled to receive pre-amplified data signals from each of the block sense amplifiers 24 in the row via a plurality of block data lines 30.
The IC memory device 10 also includes an address buffer (not shown) coupled to each of the decoders 16 and 20 of each array block row 14 for accessing memory cells (not shown) of the array blocks 12 wherein the address buffer is coupled to receive address data from an external memory controller (not shown) via designated ones of I/O pads 15. When a memory cell (not shown) of an array block 12 is selected for reading, a low level data signal is generated and transmitted via data lines 26 to a corresponding block sense amplifier 24 for amplification. The block sense amplifiers 24 generate pre-amplified data signals which are transmitted to the global sense amplifier 28. Global output lines 31 connect the global sense amplifiers 28 to particular ones of the I/O pads 15 for outputting the amplified memory data signals from the IC memory device 10. The architecture of the depicted IC memory device 10 dictates the physical layout of components of the circuit and in particular, the physical area occupied by each array block row 14 necessitates the use of long metallization lines for implementing the block data lines 30 and global output lines 31.
The architecture of the depicted prior art memory device also does not allow for optimal memory access performance because of the necessity of long metallization lines for implementing the block data lines 30 and global output line 31. Long metallization lines cause increased attenuation of data signals which causes an increase in memory access times.
The architecture of the depicted prior art memory device also does not allow for optimal memory cell density. Because the depicted architecture requires a corresponding column decoder 14 for addressing memory cells (not shown) of each array block 12, an excessive amount of chip real estate of the IC memory device 10 is occupied by column decoding circuitry. Therefore, the overall memory cell density of the IC memory device 10 is limited in part due to the use of a separate corresponding column decoder for addressing the memory cells of each array block 12.
FIG. 2 shows a block diagram at 40 illustrating a first exemplary prior art array block 12 (FIG. 1) including a plurality of memory cells 42 arranged in a number of rows 44 and columns 46. The memory cells 42 may be, for example, static RAM (SRAM) cells. Each memory cell in a row is coupled to a word line 48 adapted to receive a row address signal from a corresponding output of the row decoder 16 via a corresponding one of the row address lines 18. The depicted array block also includes a plurality of bit line pairs each of which includes a primary bit line 52 and a complementary bit line 54. Each of the bit line pairs is used to address a cell column 46 of the array block 12. The total number of word lines 48 and bit line pairs varies with the total capacity of the memory cell array. The depicted array includes M columns 46 designated COLUMN.sub.-- 0, COLUMN.sub.-- 1, . . . COLUMN.sub.-- M-1.
Each memory cell 42 includes a first data port 41 connected to a corresponding one of the bit lines 52, a second data port 43 connected to a corresponding one of the complementary bit lines 54, and a word select port 45 connected to receive a row select signal from a corresponding one of the word lines 48. Where the memory cells 42 are SRAM cells, the first and second data ports 41 and 43 are connected to access transistors (not shown) of the cells 42 which include a flip-flop device, for showing data, coupled with the access transistors.
A column multiplexer 60 includes multiplexer input ports each coupled with a corresponding one of the bit line pairs for selecting cell columns 46 of the array 12. The column multiplexer includes M column gate blocks 62 each of which is coupled with a corresponding one of the bit line pairs of the array. Each of the M column gate blocks 62 includes a primary transfer gate 64 and a complementary transfer gate 66. Each primary transfer gate 64 includes a source 67 connected to a corresponding one of the primary bit lines 52, a drain 68 connected to a primary input line 70 of a corresponding one of the block amplifiers 24 via ones of the data lines 26, and a gate 72 connected to receive a corresponding one of column select signals designated CS.sub.-- 0, CS.sub.-- 1, . . . CS.sub.-- M-1 from the column decoder 20 via a corresponding one of the column select lines 22. Each complementary transfer gate 66 of each M column gate blocks 62 includes a source 77 connected to a corresponding one of the complementary bit lines 54, a drain 78 connected to a complementary input line 80 of the corresponding block amplifier 24 via ones of the data lines 26; and a gate 82 connected to the gate 72 of the corresponding primary transfer gate 64 to receive the corresponding one of the column select signals CS.sub.-- 0, CS.sub.-- 1, . . . CS.sub.-- M-1.
Each memory cell 42 of array 12 is addressable by row decoder 16, via one of the word lines 48, and by column decoder 20 via a corresponding one of the column select lines 22. Accessing one of the memory cells 42 includes releasing stored charge which represents stored data. Upon reading from a selected memory cell, a data signal is generated as a voltage potential gradually develops between the corresponding primary and complementary bit lines 52, 54. The data signal is provided to the primary and complementary inputs 70 and 80 of the block sense amplifier 214 which amplifies the data signal to provide a pre-amplified data signal across primary and complementary outputs 86 and 88 of the amplifier.
FIG. 3 shows a detailed schematic block diagram at 100 of a second exemplary array block 12 (FIG. 1) including a plurality of dynamic RAM (DRAM) memory cells 102 arranged in a number of rows and columns 104, wherein the rows include a plurality of even rows 106 and a plurality of odd rows 108. Each DRAM cell 102 includes: a cell capacitor 110 having a first terminal 112 connected to ground, and a second terminal 114; and an access transistor 116 having a source 118 connected to the second terminal 114 of the cell capacitor, a cell drain 120, and a cell gate 122. Each DRAM cell 102 of each even row 106 has it's cell drain 120 connected to a corresponding one of the primary bit lines 128, and it's cell gate 122 connected to a corresponding one of even row word lines 130. Each DRAM cell 102 of each odd row 108 has it's cell drain 120 connected to a corresponding one of complementary bit lines 132 and it's cell gate 122 connected to a corresponding one of odd row word lines 134.
Each column 104 of the depicted array block further includes a column amplifier (or array amplifier) 140 providing amplification of data signals developed by each memory cell 102 of the column. Each column amplifier 140 includes a first data port 142 connected to provide a primary signal to a corresponding one of primary bit lines 128, a second data port 144 connected to provide a complementary signal to a corresponding one of complementary bit lines 132, a first control input 146 connected to a first amplifier control line 148 and a second control input 150 connected to a second amplifier control line 152. Each column amplifier 140 typically includes an amplifier device which is enabled by pulling control line 148 to a high voltage level and by pulling control line 152 to ground.
The depicted array block 12 also includes the column multiplexer 60 for selecting columns 104 of the array block wherein each primary transfer gate 64 has its source 67 connected to a corresponding one of the primary bit lines 128, and each corresponding transfer gate 66 has its source 77 connected to a corresponding one of the complementary bit lines 132. Columns 104 of the depicted array block are selected in the same manner as described for the array block of FIG. 2.
In summary, conflicting design goals for semiconductor memory devices include minimizing power consumption while maximizing storage capacity, or memory cell density. As the size of a memory device increases, the length of metallization lines for transmitting data signals increases and the data signals read from each memory cell suffer increased attenuation. Also, as memory cell density increases, the number of memory cells coupled to each metallization line increases causing an increased loading on each metallization line. As power supply levels decrease, the amplitudes of data signals read from memory cells become smaller and more difficult to sense.
If bit line resistance and equalization current are not considered, the time (.DELTA.t) required to build up a differential voltage potential (.DELTA.V) between voltages on corresponding primary and complementary bit line pairs, roughly follows relationship (1), below, EQU .DELTA.t=C.sub.BL * .DELTA.V/i.sub.CELL (1)
where C.sub.BL is the bit line capacitance and i.sub.CELL is the memory cell current.
The amplitude of a signal transmitted via one of the bit line pairs is proportional to the level of the power supply (not shown) used in the device 10. The overall resistance and capacitance of each of the bit line pairs increases with the length of the bit lines. As the resistance of each of the bit lines is increased, the amount of power lost to impedance increases. As expressed in Relationship (1), above, the rate of change of voltage potential, .DELTA.V, across one of bit line pairs is proportional to the cycle time, .DELTA.t. Therefore, as cycle time (.DELTA.t) is decreased beyond a certain threshold, the peak voltage potential reached across a bit line pair during a single cycle of a memory array decreases. As the cycle time is decreased, the peak voltage of the data signal may not be strong enough to be sensed during a cycle time. As a result, the minimum cycle time of memory array is limited by the time required to sense the voltage potential across one of the bit line pairs during a single cycle. Therefore, the minimum access time for sensing data in one of the memory cells of memory array is limited by the time required to sense the voltage potential across one of bit line pairs during a single cycle. Therefore, it is desirable to maximize the voltage potential across each of bit line pairs in order to sense the voltage potential across the bit line pairs. Another problem with low amplitude data signals is that the sense amplifying process becomes less stable and more likely to fail.
When the power supplied by a power supply is increased, and the length of bit line pairs is decreased, the potentials between bit line pairs is typically increased. Also, the slew rate of voltage change of the sense amplifier decreases as the power supply level is decreased and the length of bit line pairs is increased. The result of decreasing the power supply level and increasing the length of bit line pairs is that a longer time is required to access the contents of each of memory cells.
It is an object of the present invention to provide an IC memory device architecture wherein memory cell density is optimized and sensing speed maximized while the power supply of the device is scaled down.
It is a further object of the present invention to provide an IC memory device architecture utilizing intermediate sense amplifiers to maximize the data rate with reduced routing complexity.
The present invention provides a memory architecture and method for sensing data from memory cells to resolve the above stated problems. Methods according to principles of the present invention may be applied to any type of memory device.